Connict Miss Elimination by Time-stride Prefetch 1

Many hardware cache prefetching mechanisms have been proposed to improve cache per formance Most of them rely on spatial locality prediction based on continuously monitoring miss addresses While this kind of spatial locality prediction is useful in reducing the num ber of capacity and compulsory misses it may not be e ective in reducing the number of con ict misses This paper presents the design implementation and performance evalua tion of a hardware cache prefetching mechanism to reduce the number of con ict misses We introduce the concept of time stride the stride in time which allows us to capture the characteristics of con ict misses The stride is used to predict when an address will miss again and a prefetch scheduler is used to determine the time to issue a prefetch request to eliminate a future miss Results obtained via trace driven simulations show that our technique can eliminate as many as fourty percent of total number of cache misses in some applications Experiments show that our technique can function in tandem with spatial local ity based hardware prefetch mechanisms such as stride prefetcher to greatly improve cache performance Comparison with victim cache another hardware con ict miss elimination mechanism shows that our technique and victim cache have comparable ability in con ict miss elimination